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FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation
August 2006
FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation
Features
7.6MHz 5th-order Y,C filters with composite summer 14dB notch at 4.425MHz to 4.6MHz for sound trap
Description
The FMS6406 is a dual Y/C 5th-order Butterworth lowpass video filter optimized for minimum overshoot and flat group delay. The device also contains a summing circuit to generate filtered composite video, an audio trap and group delay compensation circuit. The audio trap removes video information in the spectral location of the subsequent RF audio carrier. The group delay circuit predistorts the signal to compensate for the inherent receiver IF filter's group delay distortion. In a typical application, the Y and C input signals from DACs are AC-coupled into the filters. Both channels have DC-restore circuitry to clamp the DC-input levels during video sync. The Y and C channels use separate feedback clamps. The clamp pulse is derived from the Y channel. All outputs are capable of driving 2Vpp, AC or DC-coupled, into either a single or dual video load. A single video load consists of a series 75W impedance matching resistor connected to a terminated 75W line, this presents a total of 150W of loading to the part. A dual load would be two of these in parallel which would present a total of 75W to the part. The gain of the Y, C and CV signals is 6dB with 1Vpp input levels. All video channels are clamped during sync to establish the appropriate output voltage reference levels.
capable of handling stereo 50dB stopband attenuation at 27MHz on Y, C, and CV outputs Better than 0.5dB flatness to 4.2MHz on Y, C, and CV outputs Equalizer and notch filter for driving RF modulator with group delay of -180ns No external frequency selection components or clocks < 5ns group delay on Y, C, and CV outputs AC coupled inputs AC or DC coupled outputs Capable of PAL frequency for Y, C, CV Continuous Time Low Pass Filters <1.4% differential gain with 0.7 differential phase on Y, C, and CV channels Integrated DC restore circuitry with low tilt
Applications
Cable set-top boxes Satellite set-top boxes DVD players
Block Diagram
Sync Strip Reference and Timing
VCC
7
YIN
1
6dB
8
YOUT
gM 250mV
+
6
CV OUT EQ_NOTCH
+
gM 250mV 6dB
Notch Group Delay
2
CIN 4
5 3
COUT
GND
Ordering Information
Part Number
FMS6406CS FMS6406CSX
Package
SOIC-8 SOIC-8
Pb-Free
Yes Yes
Operating Temp Range
0C to +70C 0C to +70C
Packaging Method
Tube Tape and Reel
(c) 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6406 Rev. 4.0.4
FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation
FMS6406 Pin Configuration
YIN EQ_NOTCH GND CIN
Pin Assignments
Pin# Pin
YIN
Type
Input
Description
Luminance (Luma) Input: In a typical system, this pin is connected to the Luma or composite video output pin from the external video encoder. Composite video output to RF modulator/driver. Ground Chrominance (Chroma) Input: In a typical system, this pin is connected to the Chroma output pin from the external video encoder. Filtered Chrominance Video Output from the CIN channel. Composite Video Output: This pin is the sum of YOUT and COUT. +5V supply. Filtered Luminance Video Output from the YIN channel.
1 2 3 4
8
YOUT VCC CVOUT COUT
1
FMS6406 8-pin SOIC
7 6 5
2 3 4
EQ_NOTCH GND CIN
Output Input Input
5 6 7 8
COUT CVOUT VCC YOUT
Output Output Input Output
(c) 2006 Fairchild Semiconductor Corporation
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FMS6406 Rev. 4.0.4
FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation
Absolute Maximum Ratings
The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table defines the conditions for actual device operation.
Parameter
VCC Analog and Digital I/O Output Channel - Any One Channel (Do Not Exceed)
Min.
-0.3 -0.3
Max.
6 VCC + 0.3 100
Unit
V V mA
Notes: Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if operating conditions are not exceeded.
Reliability Information
Parameter
Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Thermal Resistance (qJA), JEDEC Standard Multi-layer Test Boards, Still Air 115 -65
Min.
Typ.
Max.
150 +150 300
Unit
C C C C/W
Recommended Operating Conditions
Parameter
Operating Temperature Range VCC Range GND
Min
0 +4.75
Typ
+5.0 0
Max
70 +5.25
Unit
C V V
(c) 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6406 Rev. 4.0.4
FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation
Electrical Characteristics
Tc = 25C, Vi = 1Vpp, VCC = 5V, all inputs AC-coupled with 0.1F, all outputs are AC-coupled with 220F into 150, referenced to 400kHz; unless otherwise noted. Symbol Parameter
ICC AVYCCV AVEQ Csync Ysync CVsync EQsync TCLAMP fFLAT fC fSB Vi ISC dG dq THD XTALK PSRR SNR Supply Current1 Low Frequency Gain (YOUT, COUT, CVOUT) Low Frequency Gain (EQ_NOTCH)1 COUT Output Level (during Sync)
1 1
Conditions
VCC no load at 400kHz at 400kHz Sync present on YIN (after 6dB gain) Sync present on YIN (after 6dB gain)
1
Min
50 5.8 5.7 1.0
Typ Max Units
80 6.0 6.0 1.1 0.35 0.35 0.35 5 110 6.2 6.4 1.3 0.5 0.5 0.5 0.5 mA dB dB V V V V ms dB MHz dB Vpp mA 3 1.5 % % dB dB dB dB dB ns 5 2 102 10 -165 105 -165 1 0.75 0.5 0.5 ns ns % ns ns % ns % % dB dB dB dB dB 35 ns
YOUT Output Level (during Sync)1 CVOUT Output Level (during Sync) EQ_NOTCH Output Level (during Sync)1 Clamp Response Time (Y Channel) Gain Flatness to 4.2MHz2 (YOUT, COUT, CVOUT) -3dB Bandwidth1 Stopband Attenuation (YOUT, COUT, CVOUT)
1
Sync present on YIN (after 6dB gain) Sync present on YIN (after 6dB gain) Settled to within 10mV -0.5 Y, C, CV Channels at 27MHz All Channels/AC coupled Y, C, CV, EQ_NOTCH to GND Y, C, CV 6.7 40
0 7.6 50 1.4 85 1.4 0.7 0.3 -50 50
Input Signal Dynamic Range Output Short Circuit Current4 (Any One Channel) Differential Gain2 Differential Phase
2
Y, C, CV VOUT = 1.8Vpp at 3.58MHz at 3.58MHz DC NTC-7 weighting 4.2MHz lowpass NTC-7 weighting 4.2MHz lowpass
2
Output Distortion (All Channels) Crosstalk (Channel-to-Channel) PSRR (All Channels) SNR Y, C Channel SNR CV Channel2 SNR EQ_NOTCH Channel
2
70 70 65 -5 -2 98 -10 -195 95 -195
75 75 70 112 0 0 100 0 -180 100 -180 0.3 0.3
NTC-7 weighting 4.2MHz lowpass at 400kHz at 3.58MHz (NTSC) at 1MHz f = 3.58MHz (ref to YIN at 400kHz) f = 3.58MHz (ref to YIN at 400kHz) f = 3.58MHz (ref to YIN at 400kHz) f = 3.58MHz (ref to YIN at 400kHz)
1
tpd GD tSKEW tCLGCV tCLDCV GDEQ tCLGEQ tCLDEQ dGEQ dqEQ MCF AVPK Atten1 Atten2 Atten3 tPASS
Propagation Delay (Y, C, CV) Group Delay (Y, C, CV)
2
Skew Between YOUT and COUT2 Chroma-Luma Gain CVOUT1 Chroma-Luma Delay CVOUT1 Group Delay EQ_NOTCH1 Chroma-Luma Gain EQ_NOTCH1 Chroma-Luma Delay EQ_NOTCH Differential Gain2 Differential Phase Gain Peaking1 Notch Attenuation 11 Notch Attenuation 2
1 2
f = 3.58MHz (ref to YIN at 400kHz) EQ_NOTCH Channel EQ_NOTCH Channel EQ_NOTCH from 400kHz to 3.75MHz EQ_NOTCH from >3.75MHz to 4.2MHz EQ_NOTCH at 4.425MHz EQ_NOTCH at 4.5MHz EQ_NOTCH at 4.6MHz
1
Modulator Channel Flatness1,3
-0.5 -0.5 14 20 14 -35
0 0
Notch Attenuation 31 Passband Group Delay, EQ_NOTCH
f = 400kHz to f = 3MHz
Notes: 1. 100% tested at 25C. 2. Guaranteed by characterization. 3. Tested down to 400kHz, but guaranteed by design to 200kHz. 4. Sustained short circuit protection limited to 10 seconds.
(c) 2006 Fairchild Semiconductor Corporation
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FMS6406 Rev. 4.0.4
FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation
Typical Performance Characteristics
Tc = 25C, Vi = 1Vpp, VCC = 5V, all inputs AC-coupled with 0.1F, all outputs are AC-coupled with 220F into 150, referenced to 400kHz; unless otherwise noted.
10 0 -10
12
140 120 100
1
-20 -30 -40 -50
Mkr Frequency Ref 400kHz 1 2 3 6.53MHz 7.87MHz 27MHz Gain 6dB
Delay (ns)
30
Gain (dB)
80 60 40 20 0 400kHz
1 = 8.2MHz (111.35ns)
-60 400kHz
fSB = Gain(ref) - Gain(3) = 50.66dB
-3dB BW -44.66dB
-1dB BW
3
5
10
15
20
25
5
10
15
20
25
30
Figure . Frequency Response YOUT
10 0 -10
12
Frequency (MHz)
Figure . Group Delay vs. Frequency YOUT
140 120 100
1
Frequency (MHz)
-20 -30 -40 -50
Mkr Frequency Ref 400kHz 1 2 3 6.68MHz 7.87MHz 27MHz Gain 6dB
Delay (ns)
30
Gain (dB)
80 60 40 20 0 400kHz
1 = 8.2MHz (111.16ns)
-60 400kHz
fSB = Gain(ref) - Gain(3) = 50.41dB
-3dB BW -44.41dB
-1dB BW
3
5
10
15
20
25
5
10
15
20
25
30
Frequency (MHz)
Frequency (MHz)
Figure . Frequency Response COUT
10 0 -10
12
Figure 4. Group Delay vs. Frequency COUT
140 120 100
1
-20 -30 -40 -50
Mkr Frequency Ref 400kHz 1 2 3 6.53MHz 7.72MHz 27MHz Gain -1dB BW 6dB 3
Delay (ns)
30
Gain (dB)
80 60 40 20 0 400kHz
1 = 8.2MHz (112.84ns)
-60 400kHz
fSB = Gain(ref) - Gain(3) = 49.49dB
-3dB BW -43.49dB
5
10
15
20
25
5
10
15
20
25
30
Frequency (MHz)
Frequency (MHz)
Figure . Frequency Response CVOUT
Figure 6. Group Delay vs. Frequency CVOUT
(c) 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FMS6406 Rev. 4.0.4
FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation
Typical Performance Characteristics
Tc = 25C, Vi = 1Vpp, VCC = 5V, HD/N_SD = 0, RSOURCE = 37.5, all inputs AC-coupled with 0.1F, all outputs are AC-coupled with 220F into 150, referenced to 400kHz; unless otherwise noted.
10 5 0 -5 -10 -15 1 -20 -25 -30 -35 -40 -45 -50 1 = 4.425MHz (-16.00dB) -55 400kHz 5 10 15 1500 1000 500
1
Delay (ns)
Gain (dB)
0 -500
-1000 -1500 -2000
1 = 4.425MHz (198.47ns)
20
25
30
-2500 400kHz
5
10
15
20
25
30
Frequency (MHz)
Frequency (MHz)
Figure 7. Modulator vs. Frequency Response
0.2
Figure 8. Delay Modulator Output
0.2
NTSC
NTSC
Differential Gain (%)
0.1 0
Differential Phase (deg)
3rd 4th 5th 6th
0.1 0
-0.1 -0.2 -0.3
Min = -0.19 Max = 0.16 ppMax = 0.34
-0.1 -0.2 -0.3
Min = -0.17 Max = 0.07 ppMax = 0.25
1st
2nd
1st
2nd
3rd
4th
5th
6th
Figure 9. Differential Gain, MODOUT
-60 -65 -70
Figure 0. Differential Phase, MODOUT
200 150 100
Group Delay @ 3.58MHz = -178ns
Noise (dB)
Delay (ns)
0 1 2 4 5
-75 -80 -85 -90 -95 -100 3
50 0 -50 -100 -150 -200 0 1.0 2.0 3.0 4.0 4.6
Frequency (MHz)
Frequency (MHz)
Figure . Noise vs. Freq. Modulator Channel
Figure . Group Delay vs. Frequency
(c) 2006 Fairchild Semiconductor Corporation
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FMS6406 Rev. 4.0.4
FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation
Typical Performance Characteristics
Tc = 25C, Vi = 1Vpp, VCC = 5V, HD/N_SD = 0, RSOURCE = 37.5, all inputs AC-coupled with 0.1F, all outputs are AC-coupled with 220F into 150, referenced to 400kHz; unless otherwise noted.
2.0 1.5 1.0 0.5 0
Min = -0.00 Max = 1.17 ppMax = 1.16
NTSC
0.8
NTSC
Differential Phase (deg)
Differential Gain (%)
0.6 0.4 0.2 0
Min = -0.01 Max = 0.59 ppMax = 0.60
-0.5 1st 2nd 3rd 4th 5th 6th
-0.2 1st 2nd 3rd 4th 5th 6th
Figure . Differential Gain, VOUT
1.2 1.0
Figure 4. Differential Phase, VOUT
0.25
NTSC
NTSC
0.8 0.4 0.2 0
Min = -0.00 Max = 0.88 ppMax = 0.87
Differential Phase (deg)
0.20 0.15 0.10 0.05 0
Min = -0.04 Max = 0.21 ppMax = 0.25
Differential Gain (%)
-0.2 -0.4
-0.05 -0.10
1st
2nd
3rd
4th
5th
6th
1st
2nd
3rd
4th
5th
6th
Figure . Differential Gain, COUT
2.0 1.5 1.0 0.5 0
Figure 6. Differential Phase, COUT
0.5
NTSC
Differential Phase (deg)
Differential Gain (%)
Min = -0.00 Max = 1.42 ppMax = 1.40
NTSC Min = -0.00 Max = 0.46 ppMax = 0.46
0.4 0.3 0.2 0.1 0
-0.5 1st 2nd 3rd 4th 5th 6th
-0.1 1st 2nd 3rd 4th 5th 6th
Figure 7. Differential Gain, CVOUT
Figure 8. Differential Phase, CVOUT
(c) 2006 Fairchild Semiconductor Corporation
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FMS6406 Rev. 4.0.4
FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation
Typical Performance Characteristics
Tc = 25C, Vi = 1Vpp, VCC = 5V, HD/N_SD = 0, RSOURCE = 37.5, all inputs AC-coupled with 0.1F, all outputs are AC-coupled with 220F into 150, referenced to 400kHz; unless otherwise noted.
-60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 0 1.0 -50 -55 -60 -65
Noise (dB)
Noise (dB)
2.0 3.0 4.0 5.0
-70 -75 -80 -85 -90 -95 -100 -105 0 1.0 2.0 3.0 4.0 5.0
Frequency (MHz)
Frequency (MHz)
Figure 9. Noise vs. Frequency YOUT
-50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 0 1.0 2.0 3.0 4.0 5.0
Figure 0. Noise vs. Frequency COUT
Noise (dB)
Frequency (MHz)
Figure . Noise vs. Frequency CVOUT
(c) 2006 Fairchild Semiconductor Corporation
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FMS6406 Rev. 4.0.4
FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation
Typical Application Diagrams
FMS6406
Notch and Group Delay 4.5MHz FM Sound
2
+
Video Modulator
To Channel 3 or 4
YIN
1
5th-Order Filter
8
YOUT
+ +
CIN
6
To TV
4
5th-Order Filter
5
CVOUT to VCR
7
5V
3
COUT
Figure . AC-Coupled Application Diagram
FMS6406
Notch and Group Delay
4.5MHz FM Sound
2
+
Video Modulator
To Channel 3 or 4
YIN
1
5th-Order Filter
8
YOUT
+ +
CIN
6
To TV
4
5th-Order Filter
5
CVOUT to VCR
7
5V
3
COUT
Figure . DC-Coupled Application Diagram
(c) 2006 Fairchild Semiconductor Corporation
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FMS6406 Rev. 4.0.4
FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation
Functional Description
Introduction
This product is a two channel monolithic continuous time video filter designed for reconstructing the luminance and chrominance signals from an S-Video D/A source. Composite video output is generated by summing the Y and C outputs. The chip is designed to have AC coupled inputs and will work equally well with either AC or DC coupled outputs. The reconstruction filters provide a 5th-order Butterworth response with group delay equalization. This provides a maximally flat response in terms of delay and amplitude. Each of the four outputs is capable of driving 2Vpp into a 75 load. All channels are clamped during the sync interval to set the appropriate minimum output DC level. With this operation the effective input time constant is greatly reduced, which allows for the use of small low cost coupling capacitors. The net effect is that the input will settle to 10mV in 5ms for any DC shifts present in the input video signal. In most applications the input coupling capacitors are 0.1F. The Y and C inputs typically sink 1A of current during active video, which normally tilts a horizontal line by 2mV at the Y output. During sync, the clamp restores this leakage current by sourcing an average of 20A over the clamp interval. Any change in the coupling capacitor values will affect the amount of tilt per line. Any reduction in tilt will come with an increase in settling time.
Chrominance (C) I/O
The chrominance input can be driven in the same manner as the luminance input but is typically only a 0.7Vpp signal. Since the chrominance signal doesn't contain any DC content, the output signal can be AC coupled using as small as a 0.1F capacitor if DC-coupling is not desired.
Composite Video (CV) Output
The composite video output driver is same as the other outputs. When driving a dual load either output will still function if the other output connection is inadvertently shorted providing these loads are AC-coupled.
Equalizer/Notch (EQ_NOTCH) Output
This output is designed to drive a 600 load to 2Vpp, which will meet its primary intention of driving a modulator load.
Layout Considerations
General layout and supply bypassing play major roles in high-frequency performance and thermal characteristics. The FMS6406DEMO is a 4-layer board with a full power and ground plane. Following this layout configuration will provide the optimum performance and thermal characteristics. For optimum results, follow the steps below as a basis for high frequency layout: Include 1F and 0.1F ceramic bypass capacitors Place the 1F capacitor within 0.75 inches of the power pin Place the 0.1F capacitor within 0.1 inches of the power pin For multi-layer boards, use a large ground plane to help dissipate heat For 2-layer boards, use a ground plane that extends beyond the device by at least 0.5" Minimize all trace lengths to reduce series inductances
Luminance (Y) I/O
The typical luma input is driven by either a low impedance source of 1Vpp or the output of a 75 terminated line driven by the output of a current DAC. In either case, the input must be capacitively coupled to allow the syncdetect and DC restore circuitry to operate properly. All outputs are capable of driving 2Vpp, AC or DC-coupled, into either a single or dual video load. A single video load consists of a series 75 impedance matching resistor connected to a terminated 75 line, this presents a total of 150 of loading to the part. A dual load would be two of these in parallel which would present a total of 75 to the part. The gain of the Y, C and CV signals is 6dB with 1Vpp input levels. Even when two loads are present the driver will produce a full 2Vpp signal at its output pin.
(c) 2006 Fairchild Semiconductor Corporation
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FMS6406 Rev. 4.0.4
FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation
Mechanical Dimensions
8-Lead Outline Package (SOIC)
(c) 2006 Fairchild Semiconductor Corporation
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FMS6406 Rev. 4.0.4
FMS6406 Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM FAST(R) ActiveArrayTM FASTrTM FPSTM BottomlessTM Build it NowTM FRFETTM GlobalOptoisolatorTM CoolFETTM CROSSVOLTTM GTOTM HiSeCTM DOMETM EcoSPARKTM I2CTM i-LoTM E2CMOSTM EnSignaTM ImpliedDisconnectTM IntelliMAXTM FACTTM FACT Quiet SeriesTM Across the board. Around the world.TM The Power Franchise (R) Programmable Active DroopTM ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANARTM PACMANTM POPTM Power247TM PowerEdgeTM PowerSaverTM PowerTrench(R) QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SerDesTM ScalarPumpTM SILENT SWITCHER(R) SMART STARTTM SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TCMTM TinyLogic(R) TINYOPTOTM TruTranslationTM UHCTM UniFETTM UltraFET(R) VCXTM WireTM
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I19
P re l i m i n a r y
No Identification Needed
Full Production
Obsolete
Not In Production
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